`timescale 10ns / 1ps

module eeprom_rw_top_tb ();

    reg                    clk;
    wire                   LED;
    wire        [7:1]      PB;
    wire                   scl;
    wire                   sda;

    initial begin
        $dumpfile("output/eeprom_rw_top_tb.vcd");
        $dumpvars(0, eeprom_rw_top_tb);
    end
  
    initial begin
        clk = 0;
        #5_000_000 $stop;
    end

    always #1 clk = ~clk;
   
    eeprom_rw_top eeprom_rw_top_inst (
        .IN_CLK_50M     (clk),
        .PB             (PB),
        .LED            (LED),
        .SDA            (scl),
        .SCL            (sda)
    );

endmodule